• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention generally relates to a structure, a system and a method of manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulating materials over an etch stop layer to create a vertical stack, etching a gap through this vertical stack to expose the stop layer of etching, electrolytically plating the conductive layers using a plating material based on a desired electrical behavior of the electrical component and forming a connection between the plating materials for each of the conductive layers.
    公开号:FR3038449A1
    申请号:FR1656147
    申请日:2016-06-30
    公开日:2017-01-06
    发明作者:Christian R Bonhote；jeffrey Lille
    申请人:HGST Netherlands BV；
    IPC主号:
    专利说明:

    PHASE CHANGE SWITCH PLATED BY
    BACKGROUND OF THE INVENTION Field of the Invention [0001] Embodiments of the present invention generally relate to an electronic device and, more specifically, to a three-dimensional matrix of phase change switches or threshold switches (OTS). plated by electrolysis.
    Description of the Prior Art Close to the Invention [0002] Phase change memory (PCM) is a type of nonvolatile memory technology. PCM is a new and useful technology for memory class applications (SCM) and a serious competitor to dislodge NOR and NAND flash memory in solid-state storage applications and, in the case of NAND flash memory, disks solid state (SSD). PCM operates based on the switching of a memory cell, usually based on chalcogenides such as Ge2Sb2Tes, between two stable states, a crystalline state and an amorphous state, by heating the memory cell. To heat the memory cell, an electric current flows through the PCM cell.
    [0003] An array of PCM cells arranged in a matrix, and each PCM cell, can be coupled with a selector switch such as a threshold switch (OTS). Word (WL) and bit (BL) channels are arranged so that each memory cell can be programmed or interrogated. A row of PCM cells is activated by a single word channel WL and each of the PCM cells in this row will affect the BL bit channel to which it is electrically connected depending on the state of the PCM cells, i.e., as the cells PCM are in their state of high (amorphous) or low (crystalline) resistance.
    SUMMARY OF THE INVENTION
    [0004] Certain embodiments of the present invention generally relate to a method for making an electroless plated electrical component, comprising: depositing an etch stop layer over a substrate; depositing alternating layers of conductive and insulating materials over said etch stop layer to create a vertical stack; etching a space through this vertical stack to expose the etch stop layer; forming an electrical network for electrically connecting to a portion of said conductive layers; electroless plating on said conductive layers in said gap using a plating material based on a desired electrical behavior of the electrical component; forming an electrical connection on the plating material in said gap to allow electrical connection through said gap to said plating material; and removing the connection of said electrical network to the conductive layers.
    Some embodiments of the present invention generally relate to a structure for an electrolytically plated vertical electrical component, comprising: an etch stop layer disposed over a substrate; a vertical stack comprising alternating layers of conductive and insulating materials above this etch stop layer; wherein the vertical stack has at least one space formed therethrough, the conductive layers are electroplated using a plating material based on a desired electrical behavior of the electrical component to form a side wall of said gap, a form of said veneer is hemispherical, a thickness of said plating material is smaller than a width of said gap, a thickness of said plating material is smaller than a thickness of adjacent insulating layers in said gap; and an upper metal contact layer formed on the side wall of said gap, said plating material being between said conductive layer and said upper contact layer and said upper contact layer being connected to other adjacent electroless plated structures in said gap .
    Some embodiments of the present invention generally relate to an electrical system, comprising: a storage device comprising at least one vertical matrix, each vertical array comprising a plurality of memory cells; and a selector device for electrically accessing the plurality of memory cells in said storage device; a first metallic material for vertically connecting said vertical matrix of memory cells; and a second metallic material to be connected to a conductive material in the plane that is orthogonal to said vertical matrix of memory cells, and wherein the vertical matrix of memory cells comprises: an etch stop layer above a substrate; a vertical stack comprising alternating layers of insulating material in the plane and said conductive material in the plane above the etch stop layer, wherein the conductive and insulating layers in the plane are parallel with a surface of the substrate, the vertical stack comprising at least one space formed therethrough, and the conductive layers are plated by electrolysis using the plating material, which plating material is based on a desired electrical behavior of an electrical component to form the sidewall of said space.
    BRIEF DESCRIPTION OF THE DRAWINGS
    In order to allow the detailed understanding of the above-mentioned features of the present invention, a more detailed description of the invention will be found below, briefly summarized above, which description refers to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of this invention and should not be construed as limiting its scope, as the invention may cover other embodiments of the invention. as effective.
    Figure 1 is a block diagram of a treatment system given as an example.
    FIG. 2A illustrates a vertical stack, given as an example, of alternating layers of conductive and insulating materials, according to some embodiments of the present invention.
    FIG. 2B illustrates two vertical stacks, given as examples, of alternating layers of conductive and insulating materials, according to some embodiments of the present invention.
    Figure 2C illustrates the exemplary vertical stacks of Figure 2B with recessed layers of conductive material, according to some embodiments of the present invention.
    Figure 2D illustrates a perspective view of the exemplary vertical stacks of Figure 2C, according to some embodiments of the present invention.
    FIG. 2E illustrates the exemplary vertical stack of FIG. 2C with a plating material coupled to each of the conductive layers, according to some embodiments of the present invention.
    FIG. 2F illustrates a perspective view of the vertical stack given by way of example of FIG. 2E, according to certain embodiments of the present invention.
    Figure 2G illustrates the exemplary vertical stack of Figure 2E with a contact layer connecting each of the plating materials, according to some embodiments of the present invention.
    FIG. 2H illustrates a perspective view of the vertical stack given by way of example of FIG. 2G, according to certain embodiments of the present invention.
    Figure 21 illustrates the exemplary vertical stack of Figure 2E, wherein the conductive layers are not recessed, according to some embodiments of the present invention.
    FIG. 2J illustrates the exemplary vertical stack of FIG. 2G, in which the conductive layers are not recessed, according to some embodiments of the present invention.
    FIG. 3 illustrates an exemplary memory component using alternating layers of conductive and insulating materials, according to some embodiments of the present invention.
    For ease of understanding, identical reference numbers have been used, as far as possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without being specifically mentioned.
    DETAILED DESCRIPTION
    In the description below, reference is made to embodiments of the invention. However, it is to be understood that the invention is not limited to the specific described embodiments. Instead, any combination of the following features and elements, whether or not related to different embodiments, are contemplated to implement and apply the invention. In addition, although the embodiments of the invention may have advantages over other possible solutions and / or prior art, whether or not a particular advantage is presented by a given embodiment does not limit the scope of the invention. of the invention. Thus, the aspects, features, embodiments and advantages described hereinafter are given by way of illustration only and are not considered as elements or limitations of the appended claims unless explicitly stated in one or more claims. Likewise, any reference to "the invention" shall not be construed as a generalization of any inventive material disclosed herein and shall not be construed as an element or limitation of the appended claims unless specifically stated in a or claims.
    FIG. 1 is a functional block of a processing system 100 having a processing device 102 and a memory device 1Q4. This memory device 104 comprises memory cells that are arranged in a matrix formation of rows and columns. The processor 102 is interfaced with the memory cell array via a row decoder 106 and a column decoder 108. The individual memory cells are controlled by word channels which can extend along the rows of the array and by bit channels that can extend along the columns of the matrix. A memory cell may exist at a junction between the word and bit channels. During a read / write cycle, a row decoder selects a page of rows of memory cells to read or write to. Likewise, the column decoder selects a memory cell column address for the read / write cycle. In some embodiments of the present invention, each memory cell (e.g., at a junction between word and bit channels) may comprise at least one phase change memory (PCM) cell (e.g. phase change), a threshold switch (OTS).
    Figures 2A to 2J illustrate a structure and method for making an electrical component (eg a memory device), according to some embodiments of the present invention.
    For example, this method may comprise the deposition of an etch stop layer 202 over a substrate, on which a vertical stack of conductive and insulating layers may be deposited, as illustrated in FIG. Figure 2A. In some embodiments, the etch stop layer 202 may be made of any material that is not etched in a fluorine-containing plasma, such as chromium, a magnetic metal, or an oxide that does not is not etched in fluorine like aluminum oxide. Above the etch stop layer, alternating layers of insulating material 204 and conductive material 206 may be deposited to form a vertical stack. This vertical stack may comprise any number of insulating and conductive layers in an alternating manner as illustrated. In some embodiments, the insulative material may be silicon dioxide (SiO 2) and the conductive material may be doped silicon, molybdenum (Mo) or tungsten (W). In some embodiments, the thickness of the conductive and insulating layers may be the same. In some embodiments, the thickness 222 of the conductive layer may be smaller than the thickness 224 of the insulating layers.
    In some embodiments, a hard mask layer 208 is deposited on top of the vertical stack and is used as an etch mask. This hard mask can be made of chromium, or any material that is not etched in a plasma containing fluorine, for example.
    At this stage, one or more spaces can be formed inside the vertical stack, as illustrated in FIG. 2B. For example, a masking layer may be deposited over the hard mask 208 in a pattern, leaving exposed portions of the hard mask layer where the gap (s) are to be formed. By using etch chemistry that will etch the exposed hard mask material, the exposed portion of the hard mask can be removed. At this point, only the parts of the vertical pile where a gap is to be formed are exposed, and the other parts are covered by the hard mask material. Thus, by using etch chemistry that will etch the materials of the vertical stack, at least one space 210A and 210B may be formed in the vertical stack to the etch stop layer, exposing it. In some embodiments, a reactive ion etching (RIE) method may be used to form the spaces 210A and 210B. Optionally, the hard mask 208 can be removed after forming the spaces.
    In some embodiments, the conductive layers, now exposed to the side walls of each space 210A and 210B, may be recessed relative to the insulating layers, as shown in Figure 2C. That is, a horizontal length 226 of each of the conductive material layers 206 may be shorter than a horizontal length 228 of each of the layers of insulating material 204. For example, the side walls of each space 210A and 210B may be exposed to a plasma etching process that selectively etches the conductive layers faster than the insulating layers. Thus, recessed pockets 212 may be formed where the conductive layers are recessed relative to the walls of the spaces a greater distance than the insulating layers. These recessed pockets allow a plating material to be formed on each conductive layer (as discussed in more detail with reference to Figure 2E), so that the plating material for each conductive layer does not come into contact. with the plating material formed on an adjacent conductive layer. In some embodiments, slow wet etching may be used to form recessed pockets 212.
    [0028] FIG. 2D illustrates a perspective view of the vertical stack of conductive layers 206 and insulating layers 204 comprising the spaces 21 OA, 210B, 21 OC and 210D (210 collectively). In some embodiments, each space 210 may be conically extending through the vertical stack of conductive and insulative materials and exposing the etch stop layer. In some embodiments, each space exposes a flat surface portion of the etch stop layer, as opposed to the etching stop layer terminating at an acute point at the bottom of each gap.
    As illustrated in FIG. 2E, the conductive layers can be plated using an electroless plating process. Electroless plating is a process that uses an electric current to reduce dissolved metal cations to form a coherent metal coating on an electrode. To electrolytically plating the conductive layers, the conductive layers of the vertical stack can be coupled to an electrical network used to apply a potential to the conductive layers, acting as the cathode during electroplating. This electrical network can be temporarily formed to electrically connect all conductive layers that must contain a plating material. Each of the plating materials formed on the conductive layers may be an electroless plated device (e.g., an electroless plated phase change device). After the plating materials have been formed, the electrical network can be removed to allow electrolessly addressable plated devices. In addition, the electrical resistance from the location on the substrate where the plating material is formed and the external power supply may be similar for all devices. Electrical resistance across this (temporary) electrical network is important prior to electroless plating to obtain a similar volume and composition of all electroless plated structures.
    According to the electroless plating parameters, the plating material may have a hemispherical cross-section. Therefore, the thickest part of the electroless plated structure can be considered as the thickness of the electroless plated structure for the sake of simplicity.
    The thickness of the plating material may be smaller than the width of the gap to prevent adjacent plating material from joining it. In addition, the thickness of the insulating layers between the conductive layers is important to prevent adjacent electroless plated devices from joining in the vertical direction. Therefore, plating materials (e.g., electroless plated devices) may have a thickness that is smaller than the thickness of adjacent insulating layers. In the case where the insulating layers are not equal, the thinner insulating layer may set the limit for the thickness of the electroless plated device.
    In some embodiments, an electrolysis plating process with an aqueous bath may be used to form the plating material. In other embodiments, an ionic solution may be used during the electroless plating process. The material used to press the conductive layers (eg, the material in the bath during electroplating) may be based on a desired electrical behavior (eg a phase change material or a threshold switch (OTS)) as discussed. in more detail below. It should be noted that the hard mask layer may be removed or disconnected from any power supply so that no plating material is formed above the vertical stack. In some embodiments, each plug may be shaped to have a similar size, thickness, and composition. After the plating material has been formed, the conductive layers can be electrically insulated by disconnecting them from the power grid.
    FIG. 2F illustrates a perspective view of the vertical stack of FIG. 2E, according to certain aspects of the present invention. As illustrated, each of the plugs 220 is formed around a circumference of the spaces 210 and along one edge of the conductive layers 206.
    As illustrated in FIG. 2G, each of the plugs 220 may be connected to an upper contact strip 214, representing a dielectric barrier and an ohmic connection to an interconnecting hole which may be formed in space (FIG. for example during a subsequent processing step). The contact strip 214 may be made of a conductive material such as a metal (for example tungsten, platinum or copper). In some embodiments, the gap may be filled with a conductive material after the contact strip 214 has been formed. Figure 2H is a perspective view of the vertical stack shown in Figure 2G. As illustrated, the contact strip 214 may be formed via a conductive layer formed over each of the plating materials 220 and above the vertical stack.
    In some embodiments, the conductive layers 206 may not be recessed relative to the insulating layers 204. For example, as shown in Figure 21, a horizontal length of the conductive layers 206 is the same as horizontal length of the insulating layers 204. The plating materials 220 are formed on the conductive layers so that they do not come into contact with the plating material formed on an adjacent conductive layer. FIG. 2J illustrates the vertical stack of FIG. 21, with a contact strip 214 formed above each of the plugs 220.
    Figure 3 illustrates a plurality of memory cells in a memory device, according to some embodiments of the present invention. As illustrated, the conductive layers of adjacent spaces may be connected to form one or more strips 218 of conductive material. The junction 216 between the conductive strip 218 and the contact strip 214 comprises the plating material formed during the electroless plating process, as described with reference to FIG. 2E.
    As has been presented above, depending on the material used to press the conductive layers, the junction 216 between the conductive layer and the contact strip 214 may have different electrical properties. For example, in some embodiments, a material may be used which causes the junction 216 to have an electrical property of a phase change material, such as GeSbTe, SeTe, SiTe, SbSe, SnSe, SnTe, SnSb, GeSb , GeTe, SiSb and allies of these. An electrical behavior of a phase change material is characterized by a transition from a blocking state (e.g., an open circuit or a highly resistive state) to a resistive state, depending on whether a voltage applied to the material phase change reaches or not a certain threshold.
    In other embodiments, a plating material may be used which causes the junction 218 to have an electrical property of a threshold switch (OTS), such as GeSeBi. An OTS is a two-terminal device that goes from a blocking state (for example a very resistive state) to a conductive state depending on whether or not a voltage applied to that OTS reaches a certain threshold.
    Each band 218 may be connected to one or more selector devices (eg, switches), configured to access the junctions 216 between each of the plurality of conductive layers and the contact strip 214. In certain modes, In this embodiment, the edges of the conductive layers exposed to the sidewalls of each gap may be plated by electrolysis using a phase change material or OTS material to create one or more memory cells. Each memory cell can be controlled by components coupled with the strip 218 and the contact strip 214, which provide access to each of the junctions 216. That is, the cladding material at the junctions 216 forms memory cells of a vertical matrix, each memory cell being selected via the bands 218 using the selector devices. As illustrated, the conductive layers are orthogonal to the vertical matrix of the memory cells.
    The PCM and OTS devices disclosed herein are extensible three-dimensional arrangements. It should be understood that this description is not limited to PCM and OTS devices, but rather that it is applicable to any material with desired electrical behavior. Embodiments disclosed herein can be scaled, while having a small footprint due to their three-dimensional architecture.
    Although the above description relates to embodiments of the present invention, other embodiments of the invention may be designed without departing from the basic scope thereof, and the The basic scope of this is determined by the following claims.
    权利要求:
    Claims (20)
    [1" id="c-fr-0001]
    A method for making an electroless plated electrical component, comprising: depositing an etch stop layer over a substrate; depositing alternating layers of conductive and insulating materials over said etch stop layer to create a vertical stack; etching a space through the vertical stack to expose the etch stop layer; forming an electrical network for electrically connecting to a portion of said conductive layers; electroless plating on said conductive layers in said gap using a plating material based on a desired electrical behavior of the electrical component; forming an electrical connection on the plating material in said gap to allow electrical connection through said gap to said plating material; and removing said connection from the power grid to the conductive layers.
    [2" id="c-fr-0002]
    The method of claim 1, further comprising etching the conductive layers so that the conductive layers are recessed relative to a side wall of the gap prior to the electroless plating.
    [3" id="c-fr-0003]
    3. The method of claim 2, wherein the conductive layers are recessed relative to the side wall of the space by a distance approximately equal to a thickness of the conductive layer.
    [4" id="c-fr-0004]
    The method of claim 1, wherein the electrical behavior comprises a phase change and / or a threshold switch (OTS).
    [5" id="c-fr-0005]
    The method of claim 1, wherein etching the space through the vertical stack comprises: depositing a hard mask layer over the vertical stack; removing a portion of the hard mask layer to expose a portion of an upper surface of the vertical stack; and etching the exposed parts of the vertical stack to create the space.
    [6" id="c-fr-0006]
    The method of claim 1, wherein the etch stop layer is chromium.
    [7" id="c-fr-0007]
    The method of claim 1, wherein the conductive material is doped silicon, molybdenum (Mo) or tungsten (W) or alloys thereof.
    [8" id="c-fr-0008]
    The method of claim 1, wherein the electroless plating comprises an electrical connection between said conductive layers and an external power source through an aqueous bath.
    [9" id="c-fr-0009]
    A structure for an electrolytically plated vertical electrical component, comprising: an etch stop layer disposed over a substrate; a vertical stack comprising alternating layers of conductive and insulating materials above this etch stop layer; the vertical stack having at least one space formed therethrough, the conductive layers being plated by electrolysis using a plating material based on a desired electrical behavior of the electrical component to be formed on a side wall of said gap; a form of said plating material being hemispherical, a thickness of said plating material being smaller than a width of said space, a thickness of said plating material being smaller than a thickness of the adjacent insulating layers in said space, and a metal layer upper contact member being formed on the side wall of said gap, said plating material being between said conductive layer and said upper contact layer and said upper contact layer being connected to other adjacent electroplated structures in said gap.
    [10" id="c-fr-0010]
    10. Structure according to claim 9, wherein the conductive layers are recessed relative to the side wall of said space.
    [11" id="c-fr-0011]
    11. Structure according to claim 10, wherein the conductive layers are recessed relative to the side wall of the space by a distance approximately equal to a thickness of the conductive layer.
    [12" id="c-fr-0012]
    The structure of claim 9, wherein the electrical behavior comprises a phase change and / or a threshold switch (OTS).
    [13" id="c-fr-0013]
    The structure of claim 9, wherein the conductive material is doped silicon, molybdenum (Mo) or tungsten (W).
    [14" id="c-fr-0014]
    The structure of claim 9, wherein said space consists of a substantially vertical round hole.
    [15" id="c-fr-0015]
    An electrical system, comprising: a storage device comprising at least one vertical matrix, each vertical array comprising a plurality of memory cells; a selector device for electrically accessing the plurality of memory cells in said storage device; a first metallic material for vertically connecting said vertical matrix of memory cells; and a second metallic material connected to a conductive material in the plane which is orthogonal to said vertical matrix of memory cells, and wherein the vertical matrix of memory cells comprises: an etch stop layer over a substrate; a vertical stack comprising alternating layers of insulating material in the plane and said conductive material in the plane above the etch stop layer, the conductive and insulating layers in the plane being parallel with a surface of the substrate, the stack vertical structure comprising at least one space formed therethrough, and the conductive layers being electroplated using the plating material, the plating material being based on a desired electrical behavior of an electrical component to be formed on a side wall of said space .
    [16" id="c-fr-0016]
    The system of claim 15, wherein a thickness of the conductive layers is smaller than a thickness of the insulating layers.
    [17" id="c-fr-0017]
    The system of claim 16, wherein a horizontal length of each of the conductive material layers is shorter than a horizontal length of each layer of insulating material.
    [18" id="c-fr-0018]
    The system of claim 15, wherein the electrical behavior comprises a phase change and / or a threshold switch (OTS).
    [19" id="c-fr-0019]
    The system of claim 15, wherein the conductive material is doped silicon, molybdenum (Mo) or tungsten (W).
    [20" id="c-fr-0020]
    20. The system of claim 15, wherein the conductive layers in the plane are recessed relative to the side wall of said space.
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    法律状态:
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    优先权:
    申请号 | 申请日 | 专利标题
    US14/788,183|US9595669B2|2015-06-30|2015-06-30|Electroplated phase change switch|
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